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128m ddr sdram k4d26323 aa-gl - 1 - rev. 1.0(dec. 2001) 128mbit ddr sdram revision 1.0 december 2001 1m x 32bit x 4 banks with bi-directional data strobe and dll double data rate synchronous ram samsung electronics reserves the right to change products or specification without notice. (144-ball fbga)
128m ddr sdram k4d26323 aa-gl - 2 - rev. 1.0(dec. 2001) revision history revision 1.0(december 17, 2001) ? changed icc6 from 1.0ma to 1.2ma. revision 0.2(december 10, 2001) ? removed K4D26323AA-GL55/60 from the spec. revision 0.1(october 18, 2001) ? typo corrected revision 0.0 (october 10, 2001) - preliminary ? define mobile dedicated spec - supported vddq=1.8v as well as reduced icc6 current down to 1ma. - reduced operating current
128m ddr sdram k4d26323 aa-gl - 3 - rev. 1.0(dec. 2001) the k4d26323a is 134,217,728 bits of hyper synchronous data rate dynamic ram organized as 4 x1,048,976 words by 32 bits, fabricated with samsung ? s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 2.0gb/s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. ? 2.5v + 5% power supply for device operation ? 1.8v + 0.1v power supply for i/o interface ? sstl_18 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 3,4,5 (clock) -. burst length (2, 4, 8 and full page) -. burst type (sequential & interleave) ? full page burst length for sequential burst type only ? start address of the full page burst should be even ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? no wrtie-interrupted by read function general description features ? 4 dqs?s ( 1dqs / byte ) ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs transitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? 144-ball fbga ? maximum clock frequency up to 250mhz ? maximum data rate up to 500mbps/pin for 1m x 32bit x 4 bank ddr sdram 1m x 32bit x 4 banks double data rate synchronous ram with bi-directional data strobe and dll ordering information part no. max freq. max data rate interface package K4D26323AA-GL40 250mhz 500mbps/pin sstl_2 ( vdd=2.5v & vddq=1.8v ) 144-ball fbga K4D26323AA-GL45 222mhz 444mbps/pin K4D26323AA-GL50 200mhz 400mbps/pin
128m ddr sdram k4d26323 aa-gl - 4 - rev. 1.0(dec. 2001) pin configuration (top view) pin description ck, ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 31 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s dqs data strobe v ssq ground for dq ? s dm data mask nc no connection rfu reserved for future use mcl must connect low dqs0 vss rfu 1 thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vss vss vss vss vss vss vss vss vss rfu 2 a5 a6 dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc nc vdd vddq vddq nc vddq vddq vdd nc ba0 ba1 a0 dq3 vddq dq31 dq1 a10 a2 a1 vdd vdd vdd dq2 vddq vdd a11 a3 a9 a4 dq0 vddq vdd dq29 dq30 dq28 vddq nc vss a7 vddq vddq nc vddq vddq vdd ck a8/ap dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc vref 2 3 4 5 6 7 8 9 10 11 12 13 b c d e f g h j k l m n note: 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. vss thermal balls are optional mcl
128m ddr sdram k4d26323 aa-gl - 5 - rev. 1.0(dec. 2001) input/output functional description *1 : the timing reference point for the differential clocking is the cross point of ck and ck. for any applications using the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq ? s and dm ? s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicates the power down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras input latches row addresses on the positive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. dqs 0 ~ dqs 3 input/output data input and output are synchronized with both edge of dqs. dqs 0 for dq 0 ~ dq 7, dqs 1 for dq 8 ~ dq 15, dqs 2 for dq 16 ~ dq 23, dqs 3 for dq 24 ~ dq 31. dm 0 ~ dm 3 input data in mask. data in is masked by dm latency=0 when dm is high in burst write. dm 0 for dq 0 ~ dq 7, dm 1 for dq 8 ~ dq 15, dm 2 for dq 16 ~ dq 23, dm 3 for dq 24 ~ dq 31. dq 0 ~ dq 31 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 7 . column address ca 8 is used for auto precharge. v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommended to be left "no connection" on the device mcl must connect low must connect low
128m ddr sdram k4d26323 aa-gl - 6 - rev. 1.0(dec. 2001) block diagram (1mbit x 32i/o x 4 bank) bank select timing register a d d r e s s r e g i s t e r r e f r e s h c o u n t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r data input register serial to parallel 1mx32 1mx32 1mx32 1mx32 s e n s e a m p 2 - b i t p r e f e t c h o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register s t r o b e g e n . ck,ck addr lcke ck, ck cke cs ras cas we dmi ldmi ck, ck lcas lras lcbr lwe lwcbr l r a s l c b r ck, ck 64 64 32 32 lwe ldmi x32 dqi data strobe intput buffer dll (dqs0~dqs3)
128m ddr sdram k4d26323 aa-gl - 7 - rev. 1.0(dec. 2001) ? power-up sequence ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before vddq . - apply vddq before vref & vtt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck, ck ), apply nop and take cke to be high . 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles are required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set command with a8 to low to initialize the mode register. *1 the additional 200cycles of clock input is required to lock the dll after enabling dll. *2 sequence of 6&7 is regardless of the order. functional description power up & initialization sequence command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ precharge all banks t rp inputs must be stable for 200us ~ ~ 200 clock min. ~ ~ 2 clock min. ck,ck
128m ddr sdram k4d26323 aa-gl - 8 - rev. 1.0(dec. 2001) the mode register stores the data for controlling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. the mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. mode register set(mrs) address bus mode register cas latency a 6 a 5 a 4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 reserved 1 1 1 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. ck, ck precharge nop nop mrs nop nop 2 0 1 5 3 4 8 6 7 any nop all banks command t rp t mrd =2 t ck ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 0 rfu dll tm cas latency bt burst length ba 0 a n ~ a 0 0 mrs 1 emrs dll a 8 dll reset 0 no 1 yes test mode a 7 mode 0 normal 1 test nop
128m ddr sdram k4d26323 aa-gl - 9 - rev. 1.0(dec. 2001) the extended mode register stores the data for enabling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling dll. the extended mode register is written by assert- ing low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to normal, weak or matched impedance. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0 mrs 1 emrs figure 7. extended mode register set extended mode register set(emrs) address bus extended *1 : rfu(reserved for future use) should stay "0" during emrs cycle. a 6 a 1 output driver impedence control 0 0 n/a do not use 0 1 weak 60% vddq=2.5v 1 0 n/a do not use 1 1 matched impedance 30% vddq=1.8v rfu 1 rfu* d.i.c rfu d.i.c dll ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 mode register
128m ddr sdram k4d26323 aa-gl - 10 - rev. 1.0(dec. 2001) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2.0 w short circuit current i os 50 ma 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variations in the dc level of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. v il (mim.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v < v in < v dd is acceptable. for all other pins that are not under test v in =0v. note : recommended operating conditions(voltage referenced to v ss =0v, t j(max) =100 c) parameter symbol min typ max unit note device supply voltage v dd 2.375 2.50 2.625 v 1 output supply voltage v ddq 1.7 1.8 1.9 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v 2 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 3 dc input logic high voltage v ih(dc) v ref +0.125 - v ddq +0.30 v 4 dc input logic low voltage v il(dc) -0.30 - v ref -0.125 v 5 output logic high voltage v oh vtt+0.6 - - v i oh =-12.6ma output logic low voltage v ol - - vtt-0.6 v i ol =+12.6ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 power & dc operating conditions(sstl_18 in/out)
128m ddr sdram k4d26323 aa-gl - 11 - rev. 1.0(dec. 2001) dc characteristics note : 1. measured with outputs open. 2. refresh period is 32ms. parameter symbol test condition version unit note -40 -45 -50 operating current (one bank active) i cc1 burst lenth=2 t rc 3 t rc (min) i ol =0ma, t cc = t cc (min) 390 335 315 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 55 55 55 ma precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = t cc (min) 90 85 85 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 90 85 80 ma active standby current in in non power-down mode i cc3 n cke 3 vih(min), cs 3 vih(min), t cc = t cc (min) 215 210 210 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. 580 550 515 ma refresh current i cc5 t rc 3 t rfc (min) 245 245 235 ma 2 self refresh current i cc6 cke 0.2v 1.2 ma operating current (4bank interleaving) i cc7 burst length=4 t rc 3 t rc (min) i ol =0ma, t cc = t cc (min) 760 690 635 ma recommended operating conditions unless otherwise noted, t j(max) =100 c) 1. v id is the magnitude of the difference between the input level on ck and the input level on ck 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same note : ac input operating conditions recommended operating conditions(voltage referenced to v ss =0v, v dd =2.5v + 5%, v ddq =1.8v + 0.1v,t j(max) =100 c) parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.25 - - v input low (logic 0) voltage; dq v il - - v ref -0.25 v clock input differential voltage; ck and ck v id 0.5 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2
128m ddr sdram k4d26323 aa-gl - 12 - rev. 1.0(dec. 2001) r t =50 w output c load =30pf (fig. 1) output load circuit z0=50 w v ref =0.5*v ddq v tt =0.5*v ddq decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : ac operating test conditions (v dd =2.5v 5%, t j(max) = 100 c) parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il ) v ref +0.25/v ref -0.25 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 capacitance (v dd =3.3v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck ) c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 ) c in2 1.0 4.0 pf input capacitance ( cke, cs , ras , cas , we ) c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 ) c out 1.0 6.5 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.5 pf
128m ddr sdram k4d26323 aa-gl - 13 - rev. 1.0(dec. 2001) ac characteristics simplified timing @ bl=2, cl=4 parameter symbol -40 -45 -50 unit note min max min max min max ck cycle time cl=3 t ck - 7 - 10 5.0 10 ns cl=4 4.0 4.5 - ns cl=5 - - - ns ck high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck t dqsck -0.6 0.6 -0.7 0.7 -0.7 0.7 ns output access time from ck t ac -0.6 0.6 -0.7 0.7 -0.7 0.7 ns data strobe edge to dout edge t dqsq - 0.4 - 0.45 - 0.45 ns 1 read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in t dqss 0.85 1.15 0.8 1.2 0.8 1.2 tck dqs-in setup time t wpres 0 - 0 - 0 - ns dqs-in hold time t wpreh 0.35 - 0.3 - 0.3 - tck dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck address and control input setup t is 0.9 - 1.0 - 1.0 - ns address and control input hold t ih 0.9 - 1.0 - 1.0 - ns dq and dm setup time to dqs t ds 0.4 - 0.45 - 0.45 - ns dq and dm hold time to dqs t dh 0.4 - 0.45 - 0.45 - ns clock half period t hp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns 1 data output hold time from dqs t qh thp-0.4 - thp-0.45 - thp-0.45 - ns 1 1 3 4 6 7 tcl tck ck, ck dqs dq cs dm 2 5 tis tih 8 tds tdh 0 1 trpst trpre db0 db1 tdqss tdqsh tdqsl tch qa1 qa2 command reada writeb tdqsq t wpres t wpreh tdqsck tac
128m ddr sdram k4d26323 aa-gl - 14 - rev. 1.0(dec. 2001) note 1 : - the jedec ddr specification currently defines the output data valid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definition of tdv(=0.35tck) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is difined to account for clock duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any given cycle and is defined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax tqh timing (cl4, bl2) 1 thp ck, ck dqs dq cs 2 5 0 1 command reada tqh qa0 tdqsq(max) tdqsq(max) qa1 3 4
128m ddr sdram k4d26323 aa-gl - 15 - rev. 1.0(dec. 2001) ac characteristics (ii) K4D26323AA-GL40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 4 15 17 10 5 3 5 3 8 tck 222mhz ( 4.5ns ) 4 13 15 9 4 2 4 2 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 2 7 tck K4D26323AA-GL45 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 222mhz ( 4.5ns ) 4 13 15 9 4 2 4 2 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 2 7 tck (unit : number of clock) ac characteristics (i) note : 1. for normal write operation, even numbers of din are to be written inside dram parameter symbol -40 -45 -50 unit note min max min max min max row cycle time t rc 15 - 13 - 12 - tck refresh row cycle time t rfc 17 - 15 - 14 - tck row active time t ras 10 100k 9 100k 8 100k tck ras to cas delay for read t rcdrd 5 - 4 - 4 - tck ras to cas delay for write t rcdwr 3 2 2 - tck row precharge time t rp 5 - 4 - 4 - tck row active to row active t rrd 3 - 2 - 2 - tck last data in to row precharge @normal precharge t wr 3 - 3 - 2 - tck 1 last data in to row precharge @auto precharge t wr_a 3 - 3 - 3 - tck 1 last data in to read command t cdlr 2 - 2 - 2 - tck 1 col. address to col. address t ccd 1 - 1 - 1 - tck mode register set cycle time t mrd 2 - 2 - 2 - tck auto precharge write recovery + precharge t dal 8 - 7 - 7 - tck exit self refresh to read command t xsr 200 - 200 - 200 - tck power down exit time t pdex 1tck+tis - 1tck+tis - 1tck+tis - ns refresh interval time t ref 7.8 - 7.8 - 7.8 - us K4D26323AA-GL50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 2 7 tck
128m ddr sdram k4d26323 aa-gl - 16 - rev. 1.0(dec. 2001) 0 1 2 3 4 5 6 7 8 baa ra ra trcd activea activeb writea writeb 13 14 15 16 17 18 19 20 21 baa bab ca cb baa ca 9 10 11 12 prech baa 22 ra normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) baa ra ra bab rb rb tras trc trp trrd command dqs dq we dm ck, ck a8/ap addr (a0~a7, ba[1:0] a9,a10) activea writea da0 da1 da2 da3 simplified timing(2) @ bl=4 db0 db1 db3 da0 da1 da2 da3 db2
128m ddr sdram k4d26323 aa-gl - 17 - rev. 1.0(dec. 2001) package dimensions (144-ball fbga) unit : mm 12.0 12.0 0.8 0.8 0.25 0.05 1.40 max 0.45 0.05 0.8x11=8.8 0.40 0 . 8 x 1 1 = 8 . 8 0.40 b c d e f g h j k l m n 13 12 11 10 9 8 7 6 5 4 3 2 a1 index mark a1 index mark 0.10 max

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